1. Field of Invention
This invention relates to semiconductor integrated circuit memory devices, and more particularly to static random access memory (SRAM) devices in which some insulated gate transistors have N-type conductivity gates and other insulated gate transistors have P-type conductivity gates.
2. Related Art
Static random access memory (SEAM) cells using cross-connected complementary metal oxide semiconductor (CMOS) inverters are widely used. FIG. 1 is a schematic drawing showing a typical prior art six transistor (6T) SRAM cell 2. As shown, transistors N1, N2, N3, and N4 are N-type MOS (NMOS) transistors and transistors P1 and P2 are P-type MOS (PMOS) transistors.
As shown, transistors P1 and N1 form inverter 10. Transistor P1 is coupled between a voltage source (not shown) supplying voltage V.sub.DD (typically 5.0 or 3.5 volts, although other voltages are possible, e.g., 2.5 volts) and node A. Transistor N1 is coupled between node A and a second voltage source (not shown) supplying voltage V.sub.SS (typically a reference potential, e.g., ground). Similarly, transistor P2 is coupled between V.sub.DD and node B, and transistor N2 is coupled between node B and V.sub.SS. Inverters 10 and 12 are cross-connected such that node A is coupled to the gates of transistors P2 and N2, and node B is coupled to the gates of transistors P1 and N1. Thus if a logic low state, for example low voltage, exists at node A, transistor P2 conducts and transistor N2 does not conduct. The voltage at node B is therefore approximately V.sub.DD and a logic high state, for example high voltage, exists at node B. Due to the logic high state at node B, transistor P1 does not conduct and transistor N1 conducts. The voltage at node A is therefore approximately V.sub.SS and a logic low state exists at node A. Accordingly, the cross-connected inverter configuration is stable.
FIG. 1 also shows select transistor N3 coupled between node A and bit line 14, and select transistor N4 coupled between node B and bit line 16. The gates of transistors N3 and N4 are each coupled to word line 18. Of importance is that current flows in transistors P1 and P2 as nodes A and B, respectively, change logic state. Over time, and in large memory cell arrays, the cumulative current flows may be a significant factor in overall circuit power consumption.
FIG. 1 includes a conventional sensing circuit 20 and conventional control circuit 22. Sensing circuit 20 is coupled to bit line 14 and bit line 16. Control circuit 22 is coupled to bit line 14, bit line 16, and word line 18. Persons skilled in the art will understand that circuits 20 and 22 provide voltage sources that control writing and reading of information stored as logic states in SRAM cell 2. Circuits 20 and 22 typically contain both NMOS and PMOS transistors in a variety of conventional configurations.
In early 6T-SRAM integrated circuits the NMOS and PMOS transistors both in the memory cells, and in the control and sensing circuits, were formed with conductive polycrystalline silicon (polysilicon) gate electrodes (gates) heavily doped to N-type conductivity. Later, a "dual gate process" fabrication approach was used in which all NMOS transistors were formed with polysilicon gates having N-type conductivity and all PMOS transistors were formed with polysilicon gates having P-type conductivity. The dual gate process is typically used to form 3.3V and 2.5V technology SRAM integrated circuits. For example, PMOS transistors having P-type gates are typically used for sensing and control circuits, e.g., circuits 20 and 22, in SRAM integrated circuits because their lower threshold voltage (V.sub.T), compared with PMOS transistors having N-type gates, and higher drain-source current (I.sub.DS) increases operating speed.
FIG. 2 is a simplified cross-sectional view showing a typical CMOS structure. (Note that the overlying passivation layers and source/drain/gate electrode contacts are not shown.) The NMOS and PMOS transistors of the type shown are typically used in, for example, memory cell 2, sensing circuit 20, and control circuit 22 (FIG. 1). As shown, a conventional P-Well semiconductor area 30 (of P-type conductivity) and a conventional N-Well semiconductor area 32 (of N-type conductivity) are each formed in crystalline substrate 34. Conventional field oxide layer 36 and conventional gate oxide layer 40 are each formed on substrate 34's surface 38 as shown. Conductive gate 42A is formed on oxide layer 40 above region 30 and conductive gate 42B is formed on oxide layer 40 above region 32. In single gate technology, gates 42A and 42B are typically heavily N-type (N+) doped polysilicon. For dual gate technology, gate 42A is typically N+ polysilicon, and gate 42B is typically heavily P-type (P+) doped polysilicon.
As shown, NMOS transistor 44 is formed with N+ regions 46, and with lightly doped N-type (N-) regions 48 underlying conventional sidewall spacers 50 as shown. The N+ regions 46 are approximately aligned (self-aligned) with spacers 50 as shown. The N- regions 48 are approximately aligned (self-aligned) with gate 42A. Also shown is PMOS transistor 52 formed with P+ regions 53, and with lightly doped P-type (P-) regions 54 underlying spacers 50 as shown. The P+ regions 53 are approximately aligned (self-aligned) with spacers 50 as shown. The P- regions 54 are approximately aligned (self-aligned) with gate 42B as shown. Persons skilled in the art will be familiar with various conventional fabrication methods used to form transistors 44 and 52.
Stability is the ability of a memory cell to retain its programmed state; SRAM cell stability is desirable. In 6T SRAMs, e.g., SRAM cell 2, memory cell stability is enhanced by reducing I.sub.DS in the pull-up PMOS load transistors when these transistors conduct. One method of reducing I.sub.DS is to make the PMOS transistor "weaker" or less conductive. One way of making the PMOS weaker is to lightly dope source and/or drain regions.
U.S. Pat. No. 5,804,477 ('477 Patent), under common assignment with the present invention and incorporated herein by reference, discloses "a 6-T SRAM cell which occupies less chip area, [and] has improved write speed and improved latch-up immunity." See U.S. Pat. No. 5,804,477, col. 3 line 66. In the '477 patent a MOS transistor is made weaker by omitting heavily doped portions of source/drain regions. As described in detail in the '477 patent, lightly doped source and/or drain regions provide increased resistance with a consequent I.sub.DS decrease and enhanced SRAM stability.
The '477 patent further discloses a range of dopant concentration ratios between source/drain regions and the substrate region in which the source/drain regions are formed. For example, referring to FIG. 2, if N-Well 32 has a particular dopant concentration, and if the P- source/drain regions 54 comprised the entire source/drain regions, the P- regions 54 would have a dopant concentration of 1 to 2.5 times the particular dopant concentration of N-Well 32. Such a range of ratios also applies to NMOS transistors formed in P-wells.
Although the '477 patent demonstrates lowered I.sub.DS and improved stability over previously known 6T SRAMs, further I.sub.DS reductions and enhanced memory cell stability are desirable. Improved stability is especially important in low voltage memory cells, such as those operating at approximately 2.5 volts.